A number of different approaches have been developed to test for the correct operation of digital circuits. The most basic device is a logic probe which is placed in contact with each node under test. The probe includes an indicating lamp which flashes upon the transitions of a signal at the node under test, thereby indicating that a digital signal is present on the node. However, the logic probe provides no indication that the digital signal at the node is correct, i.e., the digital signal that should be present on the node if the circuit is operating correctly.
Attempts have also been made to use conventional oscilloscopes to test digital circuits. Although such techniques are satisfactory for extremely simple digital circuits, more complex digital circuits cannot be adequately tested with an oscilloscope for two basic reasons. First, the signals generated by complex digital circuits are, in themselves, extremely complex. It is thus difficult to determine what the correct signal should be, and even more difficult to compare the actual signal to the correct signal. Second, verification that the digital signal is correct requires that the signal be compared with other signals in the circuit during specific time periods. Yet it is extremely difficult to synchronize the oscilloscope to these signals in order to make such comparisons.
The limitations of oscilloscopes for digital circuit testing has spawned the development of the logic analyzer, which is basically a storage oscilloscope allowing sequentially stored signals to be compared with each other. Although such logic analyzers solve some of the problems inherent in digital circuit testing using oscilloscopes, they nevertheless are incapable of easily and quickly verifying the correct operation of digital circuits or isolating faults. Also, like oscilloscopes, they can be effectively used only by skilled testing personnel.
Although the above-described techniques are only somewhat inadequate for moderately complex digital circuits, they are hopelessly inadequate for microprocessor-based systems utilizing bus architecture. This is because it is not possible to test the outputs of specific individual hardware logic elements which are adapted to respond to a specific input in a well-defined manner. Instead, the microprocessor and the large-scale integration components with which it is connected generate complex data streams on the buses. Since a large number of devices are connected to common buses, it is not even possible to be sure of what device is generating a signal on the bus. Although short diagnostic programs can be written for microprocessor-based systems in order to trigger an oscilloscope at an appropriate point, this approach assumes that the microprocessor and associated hardware are functioning well enough to execute such programs.
Another problem associated with testing digital circuits by the above-described techniques is the requirement that the testing personnel be extremely knowledgeable, both as to the circuit under test and their training in electrical engineering. The high cost of such personnel greatly increases the expense of testing and repairing digital circuits.
As a result of the seemingly insurmountable difficulties encountered in testing microprocessor devices with conventional techniques, manufacturers of microprocessor-based devices have generally relied on board exchange servicing programs. That is, when a microprocessor device becomes inoperative, the circuit boards are exchanged for boards known to be functional until the system is once again operable. This servicing technique is satisfactory in many instances, but it is entirely unacceptable in many other instances. For example, board exchange programs inherently result in a considerable delay in making the needed repair, often resulting in unacceptable downtime. Also, some types of digital equipment are not sufficiently portable to readily allow portions of the equipment to be exchanged. Furthermore, a board exchange program results in a high board inventory and administrative expense, and some boards will function properly at a test facility but not in the field equipment.
As a result of these aforementioned problems, techniques have been developed to allow relatively unskilled personnel to quickly verify the correct operation of a digital circuit of even the most complex variety, such as microprocessor-based systems using bus architecture. Both of these techniques rely upon data compression principles in which data indicative of the parameters of a relatively complex signal occurring on a test node during a test period are reduced to a single number.
The first data compression testing technique is known as "transition counting," in which the number of changes of logic level on a test node are counted during the test period. The number of transitions is then compared to a previously recorded number indicative of the number of transitions which should occur during that period for a properly operating circuit. Transition counting is certainly more desirable than logic probe testing since it verifies not only that transitions are occurring but also that the number of such transitions is correct. Transition count testing is also more advantageous than oscilloscope or logic analyzer testing since the testing can be done by relatively unskilled personnel. Although transition counting is superior to conventional testing techniques, it nevertheless suffers from a lack of reliability since there is no guarantee that the transitions are occurring at the proper times.
An improved data compression testing technique described in U.S. Pat. No. 3,976,864 has been developed to provide a more reliable verification of correct operation than is possible with transition counting. This later technique, termed "signature analysis," derives a data word indicative of a digital signal during a test period of many clock cycles. The signature is generated by a multi-bit shift register that records the output of an exclusive OR-gate. The exclusive OR-gate has as its inputs the digital signal from the node under test and the outputs of specified stages of the shift register. The data word stored in the shift register at the conclusion of the test period is thus an indication of the test signal during each of the clock cycles in the test period. For a sixteen-bit shift register, there are 2.sup.16 (or 65,536) possible data words during any sample period. These sixteen bits may then be encoded in groups of four and applied to an indicator to generate a four-digit hexadecimal signature. The signature thus characterizes the digital signal on a particular circuit node during a predetermined sample period. Moreover, since the clock signal for the signature analyzer is derived from the circuit under test, the signature analyzer operates in synchronism with the circuit. As a result, the signature indicates the presence of transition time errors. The large number of possible signatures for a digital signal occurring over a substantial gate period results in a high probability of producing a unique signature for each node. Thus, recording the signatures of each node on a circuit which is known to be operating correctly fully characterizes a properly operating circuit. The nodes for a circuit under test can then be sampled to produce respective signatures which are compared to the signatures for the corresponding nodes of the original circuit.
Although signature analysis testing allows quick and accurate testing of even the most complex digital circuits and microprocessor-based equipment, its efficiency of use is nevertheless limited by the necessity of identifying a particular node and then manually comparing the signature obtained for that node with a reference source which lists each node. The manual comparison is generally accomplished through a variety of techniques. One technique involves a comparison of each signature and its corresponding node with a table of signatures and nodes. Alternatively, a schematic or circuit board layout annotated with signatures may be used. However, service personnel must still locate the proper test node from the pin numbers on the schematic or board layout and refer to both the signature analyzer and the schematic or board layout to manually compare the measured signature to the correct signature. This manual comparison, while substantially easier than comparing digital wave forms to each other with an oscilloscope, nevertheless involves the possibility of some error. This is particularly true where a large number of positive comparisons have been found, prompting the service personnel to expect the subsequent comparisons to be positive. Under such circumstances, service personnel can perceive the comparison as being positive even when it's not.
In an attempt to reduce the time required for manual comparisons, templates have been developed in which apertures are formed at positions corresponding to the positions of the nodes on the circuit board under test. The apertures allow access to each of the nodes, and respective signatures printed on the template adjacent the apertures allow quick and relatively error-free comparison between the actual signature for a node and the correct signature for that node. However, even this technique is free of error, the need for special templates for each circuit is undesirable, particularly where the correct signatures for a circuit are easily or frequently changed, as is the case with microprocessor devices.